1. Field of the Invention
This invention relates to computing systems, and more particularly, to efficiently limiting storage space for data with particular properties in a cache memory.
2. Background
A microprocessor may be coupled to one or more levels of a cache hierarchy in order to reduce the latency of the microprocessor's request of data in memory for a read or a write operation. Generally, a cache may store one or more blocks, each of which is a copy of data stored at a corresponding address in the system memory. Since caches have finite sizes, the total number of cache blocks is inherently bounded. Additionally, there may be a limit on the number of blocks that map to a given set in a set-associative cache. However, there may be conditions that benefit from a finer limit on a number of cache blocks associated with a given cache property than a limit offered by the cache capacity or the cache associativity. Examples of the cache property may include one or more of a coherence state, a dirty state, a source ownership state, a remote state that may be used in a non-uniform memory access (NUMA) computing system, and so forth.
Providing the finer limit on the number of cache blocks associated with the given cache property may reduce latencies for searching for the number of cache blocks and moving the number of cache blocks prior to setting the cache in a different state. The different state may be a low-power mode. Additionally, the finer limit may reduce a number of conflict misses for a set-associative or a direct-mapped cache for both cache blocks with and without the cache property.
Further, the latency for the cache to transition to a given state, such as a low-power mode, may be reduced with the finer limit. For example, to manage power consumption, chip-level and system-level power management systems typically disable portions of the chip or system when experiencing no utilization for a given time period. However, transitioning the cache to a low-power mode may be delayed until the number of cache blocks associated with the cache property are evicted and written back to lower-level memory. Without the finer limit, the transition latency may be too large. The large latency may reduce both the benefits of the power management system and the number of times the transition actually occurs despite the power management system notifications.
To allocate space for new data to be stored in the cache, such as a cache line fill following a cache miss, a cache replacement algorithm may select a given way within a given set to be replaced. If this allocation strategy does not distinguish requests associated with the cache property, then the strategy may allow a significant portion of the ways in the cache to be occupied with cache blocks associated with the cache property. Without the finer limit being utilized as previously described, operational latencies may increase, conflict misses may increase, and cache state transitions may reduce.
In view of the above, efficient methods and systems for efficiently performing data allocation in a cache memory are desired.